Crate ppv_lite86

Re-exports

• pub use self::arch::vec128_storage;
• pub use self::arch::vec256_storage;
• pub use self::arch::vec512_storage;

Modules

• soft 🔒
  Implement 256- and 512- bit in terms of 128-bit, for machines without native wide SIMD.
• types 🔒
• x86_64

Macros

• dispatch
  Generate the full set of optimized implementations to take advantage of the most important hardware feature sets.
• dispatch_light128
  Generate only the basic implementations necessary to be able to operate efficiently on 128-bit vectors on this platfrom. For x86-64, that would mean SSE2 and AVX.
• dispatch_light256
  Generate only the basic implementations necessary to be able to operate efficiently on 256-bit vectors on this platfrom. For x86-64, that would mean SSE2, AVX, and AVX2.

Traits

• AndNot
• ArithOps
  Ops that depend on word size
• BSwap
• BitOps0
  Ops that are independent of word size and endian
• BitOps32
• BitOps64
• BitOps128
• LaneWords4
  A vector composed one or more lanes each composed of four words.
• Machine
• MultiLane
  A vector composed of multiple 128-bit lanes.
• RotateEachWord32
• RotateEachWord64
• RotateEachWord128
• Store
• StoreBytes
• Swap64
  Exchange neigboring ranges of bits of the specified size
• UnsafeFrom
• VZip
  Combine single vectors into a multi-lane vector.
• Vec2
  A vector composed of two elements, which may be words or themselves vectors.
• Vec4
  A vector composed of four elements, which may be words or themselves vectors.
• Vec4Ext
  Vec4 functions which may not be implemented yet for all Vec4 types. NOTE: functions in this trait may be moved to Vec4 in any patch release. To avoid breakage, import Vec4Ext only together with Vec4, and don’t qualify its methods.
• Vector
• Words4
  A vector composed of four words; depending on their size, operations may cross lanes.
• u32x4
• u32x4x2
• u32x4x4
• u64x2
• u64x2x2
• u64x2x4
• u64x4
• u128x1
• u128x2
• u128x4