fearless_simd/core_arch/x86/
ssse3.rs

1// Copyright 2024 the Fearless_SIMD Authors
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3
4//! Access to SSSE3 intrinsics.
5
6use crate::impl_macros::delegate;
7#[cfg(target_arch = "x86")]
8use core::arch::x86 as arch;
9#[cfg(target_arch = "x86_64")]
10use core::arch::x86_64 as arch;
11
12use arch::*;
13
14/// A token for SSSE3 intrinsics on `x86` and `x86_64`.
15#[derive(Clone, Copy, Debug)]
16pub struct Ssse3 {
17    _private: (),
18}
19
20impl Ssse3 {
21    /// Create a SIMD token.
22    ///
23    /// # Safety
24    ///
25    /// The required CPU features must be available.
26    #[inline]
27    pub unsafe fn new_unchecked() -> Self {
28        Self { _private: () }
29    }
30
31    delegate! { arch:
32        fn _mm_abs_epi8(a: __m128i) -> __m128i;
33        fn _mm_abs_epi16(a: __m128i) -> __m128i;
34        fn _mm_abs_epi32(a: __m128i) -> __m128i;
35        fn _mm_shuffle_epi8(a: __m128i, b: __m128i) -> __m128i;
36        fn _mm_alignr_epi8<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i;
37        fn _mm_hadd_epi16(a: __m128i, b: __m128i) -> __m128i;
38        fn _mm_hadds_epi16(a: __m128i, b: __m128i) -> __m128i;
39        fn _mm_hadd_epi32(a: __m128i, b: __m128i) -> __m128i;
40        fn _mm_hsub_epi16(a: __m128i, b: __m128i) -> __m128i;
41        fn _mm_hsubs_epi16(a: __m128i, b: __m128i) -> __m128i;
42        fn _mm_hsub_epi32(a: __m128i, b: __m128i) -> __m128i;
43        fn _mm_maddubs_epi16(a: __m128i, b: __m128i) -> __m128i;
44        fn _mm_mulhrs_epi16(a: __m128i, b: __m128i) -> __m128i;
45        fn _mm_sign_epi8(a: __m128i, b: __m128i) -> __m128i;
46        fn _mm_sign_epi16(a: __m128i, b: __m128i) -> __m128i;
47        fn _mm_sign_epi32(a: __m128i, b: __m128i) -> __m128i;
48    }
49}
fearless_simd/core_arch/x86/ssse3.rs

fearless_simd/core_arch/x86/
ssse3.rs
