fearless_simd/core_arch/x86/
sse4_2.rs

1// Copyright 2024 the Fearless_SIMD Authors
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3
4//! Access to SSE4.2 intrinsics.
5
6use crate::impl_macros::delegate;
7#[cfg(target_arch = "x86")]
8use core::arch::x86 as arch;
9#[cfg(target_arch = "x86_64")]
10use core::arch::x86_64 as arch;
11
12use arch::*;
13
14/// A token for SSE4.2 intrinsics on `x86` and `x86_64`.
15#[derive(Clone, Copy, Debug)]
16pub struct Sse4_2 {
17    _private: (),
18}
19
20impl Sse4_2 {
21    /// Create a SIMD token.
22    ///
23    /// # Safety
24    ///
25    /// The required CPU features must be available.
26    #[inline]
27    pub unsafe fn new_unchecked() -> Self {
28        Self { _private: () }
29    }
30
31    delegate! { arch:
32        fn _mm_cmpistrm<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i;
33        fn _mm_cmpistri<const IMM8: i32>(a: __m128i, b: __m128i) -> i32;
34        fn _mm_cmpistrz<const IMM8: i32>(a: __m128i, b: __m128i) -> i32;
35        fn _mm_cmpistrc<const IMM8: i32>(a: __m128i, b: __m128i) -> i32;
36        fn _mm_cmpistrs<const IMM8: i32>(a: __m128i, b: __m128i) -> i32;
37        fn _mm_cmpistro<const IMM8: i32>(a: __m128i, b: __m128i) -> i32;
38        fn _mm_cmpistra<const IMM8: i32>(a: __m128i, b: __m128i) -> i32;
39        fn _mm_cmpestrm<const IMM8: i32>(a: __m128i, la: i32, b: __m128i, lb: i32) -> __m128i;
40        fn _mm_cmpestri<const IMM8: i32>(a: __m128i, la: i32, b: __m128i, lb: i32) -> i32;
41        fn _mm_cmpestrz<const IMM8: i32>(a: __m128i, la: i32, b: __m128i, lb: i32) -> i32;
42        fn _mm_cmpestrc<const IMM8: i32>(a: __m128i, la: i32, b: __m128i, lb: i32) -> i32;
43        fn _mm_cmpestrs<const IMM8: i32>(a: __m128i, la: i32, b: __m128i, lb: i32) -> i32;
44        fn _mm_cmpestro<const IMM8: i32>(a: __m128i, la: i32, b: __m128i, lb: i32) -> i32;
45        fn _mm_cmpestra<const IMM8: i32>(a: __m128i, la: i32, b: __m128i, lb: i32) -> i32;
46        fn _mm_crc32_u8(crc: u32, v: u8) -> u32;
47        fn _mm_crc32_u16(crc: u32, v: u16) -> u32;
48        fn _mm_crc32_u32(crc: u32, v: u32) -> u32;
49        fn _mm_cmpgt_epi64(a: __m128i, b: __m128i) -> __m128i;
50    }
51}
fearless_simd/core_arch/x86/sse4_2.rs

fearless_simd/core_arch/x86/
sse4_2.rs
