fearless_simd/core_arch/x86/
sse3.rs

1// Copyright 2024 the Fearless_SIMD Authors
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3
4//! Access to SSE3 intrinsics.
5
6use crate::impl_macros::delegate;
7#[cfg(target_arch = "x86")]
8use core::arch::x86 as arch;
9#[cfg(target_arch = "x86_64")]
10use core::arch::x86_64 as arch;
11
12use arch::*;
13
14/// A token for SSE3 intrinsics on `x86` and `x86_64`.
15#[derive(Clone, Copy, Debug)]
16pub struct Sse3 {
17    _private: (),
18}
19
20#[expect(
21    clippy::missing_safety_doc,
22    reason = "TODO: https://github.com/linebender/fearless_simd/issues/40"
23)]
24impl Sse3 {
25    /// Create a SIMD token.
26    ///
27    /// # Safety
28    ///
29    /// The required CPU features must be available.
30    #[inline]
31    pub unsafe fn new_unchecked() -> Self {
32        Self { _private: () }
33    }
34
35    delegate! { arch:
36        fn _mm_addsub_ps(a: __m128, b: __m128) -> __m128;
37        fn _mm_addsub_pd(a: __m128d, b: __m128d) -> __m128d;
38        fn _mm_hadd_pd(a: __m128d, b: __m128d) -> __m128d;
39        fn _mm_hadd_ps(a: __m128, b: __m128) -> __m128;
40        fn _mm_hsub_pd(a: __m128d, b: __m128d) -> __m128d;
41        fn _mm_hsub_ps(a: __m128, b: __m128) -> __m128;
42        unsafe fn _mm_lddqu_si128(mem_addr: *const __m128i) -> __m128i;
43        fn _mm_movedup_pd(a: __m128d) -> __m128d;
44        unsafe fn _mm_loaddup_pd(mem_addr: *const f64) -> __m128d;
45        fn _mm_movehdup_ps(a: __m128) -> __m128;
46        fn _mm_moveldup_ps(a: __m128) -> __m128;
47    }
48}
fearless_simd/core_arch/x86/sse3.rs

fearless_simd/core_arch/x86/
sse3.rs
