Vector type naming scheme: uN[xP]xL Unsigned; N-bit words * P bits per lane * L lanes
A lane is always 128-bits, chosen because common SIMD architectures treat 128-bit units of wide vectors specially (supporting e.g. intra-lane shuffles), and tend to have limited and slow inter-lane operations.
A vector composed one or more lanes each composed of four words.
A vector composed of multiple 128-bit lanes.
Exchange neigboring ranges of bits of the specified size
Combine single vectors into a multi-lane vector.
A vector composed of two elements, which may be words or themselves vectors.
A vector composed of four elements, which may be words or themselves vectors.
A vector composed of four words; depending on their size, operations may cross lanes.